Frequency modulator apparatus of phase selection type, and frequency synthesizer of phase selection type

ABSTRACT

A phase-selective type frequency modulator capable of easing the restriction on a phase range of a modulated clock signal. The phase-selective type frequency modulator includes a multiphase clock signal generating circuit  101  for generating N-phase clock signals; a control circuit  104  for sequentially activating one of first group of clock selection signals indicating a clock signal to be selected from the N-phase clock signals; an edge appearance time adjustment circuit  103  for adjusting a rising edge appearance time and/or a trailing edge appearance time of the first group of clock selection signals outputted from the control circuit  104  to output second group of clock selection signals; and a modulated clock signal generating circuit  102  for selecting one clock signal from the N-phase clock signals in accordance with an activated state of the second group of clock selection signals outputted from the edge appearance time adjustment circuit  103  to output a modulated clock signal MCK.

TECHNICAL FIELD

The present invention relates to a phase-selective type frequencymodulator and a phase-selective type frequency synthesizer capable ofreducing electromagnetic interference (hereinafter, referred to as“EMI”) in electronic equipment which transmits image data, etc.

BACKGROUND ART

With the rapid operation of electronic equipment, the EMI in theelectronic equipment becomes a problem and the reduction of the EMI isrequired. As one technology for reducing the EMI in electronicequipment, a method employing a spread spectrum clock signal has beenproposed. More specifically, jitter is intentionally generated so that apeak of a spectrum may not be generated at a particular frequency, or afrequency is varied gradually with a cycle, that provides no influenceon the operation of the circuit, for example, a cycle in a range fromseveral of kilo Hertz to several hundreds of kilo Hertz.

FIG. 17 is a functional block diagram showing a configuration of a clocksignal generator disclosed in Japanese Patent Application PublicationJP-A-2001-148690. As shown in FIG. 17, the above-mentioned clock signalgenerator has a clock generating unit 2001 for generating m-phase clocksignals S1 m having a desired frequency and phases shifted by a constantinterval between adjacent two clock signals, a selector unit 2003 forselecting one of the m-phase clock signals S1 m, and a dithering controlunit 2002 for determining the selection in the selector unit 2003. Them-phase clock signals S1 m generated in the clock generating unit 2001are supplied to the selector unit 2003 and taken out via an outputterminal 2005. To the selector unit 2003, a control signal SEL issupplied from the dithering control unit 2002. The selector unit 2003sequentially selects one of the m-phase clock signals S1 m in accordancewith the control signal SEL and thus obtained clock signal S2 can betaken out from an output terminal 2004. The dithering control unit 2002for controlling the selector unit 2003 generates a selection signal SELsuch that the spectrum of the clock signal S2 obtained at the outputterminal 2004 may spread over as wide as possible.

FIG. 18 is a circuit block diagram showing a specific configurationexample of the dithering control unit 2002. As shown in FIG. 18, thedithering control unit 2002 includes eight D-type flip-flops 2031 to2038 forming a serial ring, and three OR circuits 2041 to 2043. When onesignal of output signals S0 to S4 is at a high level, other four signalsare made to be at low level, and the high-level moves among thesesignals per cycle of a clock signal CK.

FIG. 19 is a block diagram showing a specific configuration example ofthe selector unit 2003. The selector unit 2003 includes five switchcircuits 2051 to 2055 and a buffer circuit 2056. In synchronization withthe above-mentioned output signals S0 to S4, one of five-phase clocksignals DC0 to DC4 at ΔT intervals is selected, and a modulated clocksignal is generated and outputted via the buffer circuit 2056.

FIG. 20 shows an operation waveform example of the above-mentioned clocksignal generator. As shown in FIG. 20, in a time period A, the clocksignals are selected in the order of DC0, DC1, DC2, SC3, DC4 and theperiod of the modulated clock signal S2 becomes T+ΔT. On the other hand,in a time period B, the clock signals are selected in the order of DC4,DC3, DC2, SC, DC0 and the period of the modulated clock signal S2becomes T-ΔT. Here, “T” is defined as an inverse number of a frequencyfcR of a system clock signal, and, hereinafter, “T” is used in the samesense. Since the operations in the time periods A and B are repeated,+ΔT and −ΔT are cancelled so that the modulation period T_(mod) (notshown) becomes T_(mod)=8×T. According to the above-mentioned clocksignal generator, a clock signal can be outputted in which peaks on thespectrum are spread, and the EMI can be reduced by operating theelectrical equipment employing the clock signal.

However, in the case where the above-mentioned clock signal generator isused, there is a problem as described below. The problem will beexplained by referring to FIG. 21. FIG. 21 shows the problem in theoperation of the above-mentioned clock signal generator. As shown inFIG. 21, when the edges of the m-phase clock signals S1 m (a rising edge2101 and a trailing edge 2103 are shown in FIG. 21) and the edges of theselection signal SEL overlap one another, the operations of the switchcircuits 2051 to 2055 (switching between “0” and “1”) provided in theselector unit 2003 as shown in FIG. 19 becomes defective and thewaveform of the modulated clock signal becomes deteriorated. That is,within 360 degrees as a clock phase corresponding to one period of thesystem clock signal as shown in FIG. 21 (the range shown by an arrow), arange of a clock phase of the system clock signal that can be actuallychanged is restricted to a range obtained by subtracting a range inconsideration of a predetermined interval from 180 degrees, i.e., lessthan 180 degrees.

Here, referring to FIGS. 22A to 22C, the relationship between themodulation period and the spectrum intensity of the clock signal will beexplained. FIG. 22A shows the relationship between the spectrumintensity and the frequency when the clock signal is not modulated. FIG.22B shows the relationship between the spectrum intensity and thefrequency when the modulation period is short, that is, 1/Tmod is large.FIG. 22C shows the relationship between the spectrum intensity and thefrequency when the modulation period is long, that is, 1/Tmod is small.Here, “Tmod” represents a modulation period and “T” is an inverse numberof the frequency f_(CK) of the system clock signal.

As shown in FIG. 22A, when the clock signal is not modulated, a spectrumpeak 2201 is observed in the position where f=1/T. In the case where theclock signal is modulated so that the modulation clock frequency maybecome T−ΔT and T+ΔT for spreading the spectrum as shown in FIG. 22A,peaks are expected to appear at frequencies f=1/(T+ΔT) and f=1/(T−ΔT).However, almost all spectrum components at frequencies f=1/(T+ΔT) andf=1/(T−ΔT) are concentrated at the peak 2201 at a frequency f=1/T whenthe modulation period is short, i.e., 1/Tmod>Δf, and the powerdispersion never occurs as shown in FIG. 22B. Because, according to thenature of the Fourier transform, as to the waveform changing with acycle of 1/Tmod, peaks appear at frequency intervals of 1/Tmod. On theother hand, when the modulation period is long as shown in FIG. 22C,i.e., 1/Tmod<Δf, the spectrum components at frequencies f=1/(T+ΔT) andf=1/(T−ΔT) appear as peaks. That is, in addition to the peak 2201 at thefrequency f=1/T, a peak 2217 and a peak 2215 appear between thefrequencies f=1/(T+ΔT) and f=1/(T−ΔT) at frequency intervals of 1/Tmod.With the power dispersion, the intensity of the peak 2201 at thefrequency f=1/T becomes lower compared to the intensity of the peak 2201as shown in FIGS. 22A and 22B, and the occurrence of power dispersion isseen.

Considering a condition under which the modulation effect is seen, it isnecessary that the frequency interval at which the peaks appear isshorter than the frequency interval between 1/T and 1/(T+ΔT). That is,the following expression (1) is required to hold.1/Tmod<ABS(1/T−1/(T±ΔT))≅ΔT/T ²   (1)Where ABS(X) represents an absolute value of X.

Here, given that the number of phases of multiphase clock signals is N,the modulation period Tmod is expressed by the following expression (2).Tmod=2N×T   (2)

With the expressions (1) and (2), the following expression (3) can beintroduced.T/2<N×ΔT   (3)

Here, N×ΔT corresponds to the range in which the phase is valuable inthe circuits as shown in FIG. 17-19, and a phase valuable range of atleast 180 degrees is required as described above.

DISCLOSURE OF THE INVENTION

Accordingly, in view of the above-mentioned points, an object of thepresent invention is to provide a phase-selective type frequencymodulator and a phase-selective type frequency synthesizer capable ofeasing the restriction on a phase range of a modulated clock signal.

In order to solve the above-mentioned problems, a phase-selective typefrequency modulator according to one aspect of the present inventionincludes: multiphase clock signal generating means for generatingN-phase clock signals having phase differences from each others; controlmeans for sequentially activating one of first group of clock selectionsignals indicating a clock signal to be selected from the N-phase clocksignals outputted from the multiphase clock signal generating means, thefirst group of clock selection signals corresponding to the N-phaseclock signals; edge appearance time adjusting means for adjusting arising edge appearance time and/or a trailing edge appearance time ofthe first group of clock selection signals outputted from the controlmeans to output second group of clock selection signals corresponding tothe N-phase clock signals outputted from the multiphase clock signalgenerating means; and modulated clock signal generating means forselecting one clock signal from the N-phase clock signals in accordancewith an activated state of the second group of clock selection signalsoutputted from the edge appearance time adjusting means to output theselected clock signal as a modulated clock signal.

Further, a phase-selective type frequency synthesizer according to oneaspect of the present invention includes: control means for sequentiallyactivating one of first group of clock selection signals indicating aclock signal to be selected from N-phase clock signals having phasedifferences from each others, the first group of clock selection signalscorresponding to the N-phase clock signals; edge appearance timeadjusting means for adjusting a rising edge appearance time and/or atrailing edge appearance time of the first group of clock selectionsignals outputted from the control means to output second group of clockselection signals corresponding to the N-phase clock signals; modulatedclock signal generating means for selecting one clock signal from theN-phase clock signals in accordance with an activated state of thesecond group of clock selection signals outputted from the edgeappearance time adjusting means to output the selected clock signal;phase comparing means for comparing a phase of a reference clock signaland a phase of the clock signal selected by the modulated clock signalgenerating means; and multiphase clock signal generating means forgenerating the N-phase clock signals based on a comparison result in thephase comparing means and outputting one of the N-phase clock signals asa modulated clock signal.

According to the present invention, since the restriction on the phaserange of the modulated clock signal can be eased, the EMI can be furtherreduced.

BRIEF DESCRIPTION OF THE DRAWINGS

Advantages and features of the present invention will be clear byconsidering the following detailed description and the drawings inrelation. In these drawings, the same reference numerals indicate thesame component elements.

FIG. 1 is a block diagram showing a configuration of a phase-selectivetype frequency modulator according to a first embodiment of the presentinvention;

FIG. 2 is a block diagram showing a configuration of a phase-selectivetype frequency synthesizer according to the first embodiment of thepresent invention;

FIG. 3 is a block diagram showing a configuration example of amultiphase clock signal generating circuit as shown in FIG. 1;

FIG. 4 is a block diagram showing a configuration example of amultiphase VCO as shown in FIG. 2;

FIG. 5 shows a configuration example including a modulated clock signalgenerating circuit and an edge appearance time adjustment circuit asshown in FIG. 1;

FIG. 6 shows a configuration example including a modulated clock signalgenerating circuit and an edge appearance time adjustment circuit asshown in FIG. 2;

FIGS. 7A and 7B show configuration examples of a switch circuit in FIG.5;

FIG. 8 shows a modified example of the modulated clock signal generatingcircuit and the edge appearance time adjustment circuit as shown in FIG.5 or 6;

FIG. 9 is a timing chart for explaining an operation of the modulatedclock signal generating circuit and the edge appearance time adjustmentcircuit;

FIG. 10 is a timing chart for explaining an operation of the modulatedclock signal generating circuit and the edge appearance time adjustmentcircuit;

FIG. 11 is a block diagram showing a configuration example of a controlcircuit as shown in FIG. 1 or 2;

FIG. 12 shows an up/down ring register as shown in FIG. 11;

FIG. 13 is a block diagram showing another configuration example of thecontrol circuit as shown in FIG. 1 or 2;

FIG. 14 is a timing chart showing an operation of the control circuit asshown in FIG. 13;

FIG. 15 is a block diagram showing a configuration of a three-valued ΔΣmodulator as shown in FIG. 11;

FIG. 16 is a block diagram showing a configuration of a phase-selectivetype frequency modulator according to a second embodiment of the presentinvention;

FIG. 17 is a block diagram showing a configuration of a conventionalclock signal generator;

FIG. 18 is a block diagram showing a configuration example of adithering control unit in FIG. 17;

FIG. 19 is a block diagram showing a configuration of a selector unit inFIG. 17;

FIG. 20 is an operation waveform chart of the clock signal generator inFIG. 17;

FIG. 21 is a diagram for explaining a problem of the clock signalgenerator in FIG. 17 in view of the operation waveform; and

FIG. 22 is a diagram for explaining a problem of the clock signalgenerator in FIG. 17 in view of spectrum spread.

BEST MODE FOR CARRYING OUT THE INVENTION

In a phase-selective type frequency modulator and a phase-selective typefrequency synthesizer according to the present invention, in order togenerate a modulated clock signal in which the restriction of phasevaluable range is eased to reduce the EMI, a circuit is formed such thata rising edge appearance time and/or a trailing edge appearance time ofone clock signal selected from N-phase clock signals and a rising edgeappearance time and/or a trailing edge appearance time of a clockselection signal for selecting the clock signal may have time lag andmay not overlap one another.

Here, in the case where a number “N” of phases of the N-phase clocksignals is an integer number equal to or more than four, thephase-selective type frequency modulator and the phase-selective typefrequency synthesizer according to the present invention exert effects.

More specifically, when a modulated clock signal is generated byselecting one clock signal (referred to as a “first clock signal”) fromthe N-phase clock signals from 1 to N having different phases, as aclock selection signal for selecting the first clock signal, a secondclock selection signal is generated which has the edge appearance timeadjusted based on another clock signal (referred to as a “second clocksignal”) having a different phase from the first clock signal among theN-phase clock signals and which the first clock signal indicates to beselected. According to the activated state of the second clock selectionsignal (e.g., high-level or low-level), one of the N-phase clock signalsCK1 to CKN is selected and the selected clock signal is outputted as amodulated clock signal.

Thereby, the rising edge appearance time and/or the trailing edgeappearance time of the first clock signal and the rising edge appearancetime and/or the trailing edge appearance time of the second group ofclock selection signals for selecting the first clock signal can bearbitrarily shifted.

Based on the above consideration, a phase-selective type frequencymodulator according to embodiments of the present invention will beexplained by referring to the drawings as below.

FIG. 1 shows a configuration of a phase-selective type frequencymodulator according to a first embodiment of the present invention. Asshown in FIG. 1, a phase-selective type frequency modulator 100according to the first embodiment of the present invention includes amultiphase clock signal generating circuit 101 for generating multiphaseclock signals, a modulated clock signal generating circuit 102 forperforming modulation operation by selecting one clock signal from themultiphase clock signals, an edge appearance time adjustment circuit103, and a control circuit 104 having a clock selection signalgenerating circuit 105 and a control logic circuit 106 for controllingit. A number “N of phases of the multiphase clock signals is, forexample, 6, 12, or the like. The modulated clock signal generatingcircuit 102 outputs a selected clock signal SELCLK as a modulated clocksignal MCK.

FIG. 2 shows a configuration of a phase-selective type frequencysynthesizer employing the phase-selective type frequency modulator inFIG. 1. A phase-selective type frequency synthesizer 110 modulates aninputted reference clock signal (REFCLK) 111 to output it as a modulatedclock signal 120. The phase-selective type frequency synthesizerincludes a phase comparison circuit 115 having a phase detector (PD)112, a charge pump 113, and a loop filter 114 such as a low pass filter(LPF), and a multiphase (N-phase) voltage controlled oscillator (VCO)116. Furthermore, the phase-selective type frequency synthesizerincludes a modulated clock signal generating circuit 102, an edgeappearance time adjustment circuit 103, and a control circuit 104 havinga clock selection signal generating circuit 105 and a control logiccircuit 106 similar to those shown in FIG. 1. The output of themodulated clock signal generating circuit 102 is controlled by the phasecomparison circuit 115 which compares a phase of a clock signal fed backvia a divider 117 and a phase of the reference clock signal (REFCLK)111. A clock signal CK1 as one of the output of the multiphase VCO 116is divided in a divider 118, and the modulated clock signal 120 isoutputted which has a frequency modulated into a desired value.

The modulated clock signal generating circuit 102 selects one of N-phaseclock signals outputted from the multiphase VCO 116 to output it as aselected clock signal SELCLK. By comparing a phase of the feed backsignal and a phase of the reference clock signal (REFCLK) 111 in thephase comparison circuit 115 and controlling the output of the modulatedclock signal generating circuit 102, the modulated clock signal 120,which has a frequency modulated into a desired value, is generated basedon the clock signal CK1 as one of outputs of the multiphase VCO 116.

In the above-mentioned configuration, when the selection in the selectorof the modulated clock signal generating circuit 102 is not changed, thefrequency of the modulated clock signal is expressed by the followingexpression.f 0 =f _(REFCLK) ·M/N

When the selection in the selector is shifted, for example, backwardlyone at a time, the frequency of the modulated clock signal is controlledto be f_(max)=f0·13/12. Oppositely, when the selection in the selectoris forwardly shifted, for example, forwardly one at a time, thefrequency of the modulated clock signal is controlled to bef_(min)=f0·11/12. By mixing the manners of shifting selection in theselector, the frequency of the modulated clock signal can be controlledto be an arbitrary value between f_(min) and f_(max).

By controlling the manners of shifting selection in the selector byusing delta sigma modulation according to frequency data, it is possibleto cause the frequency of the modulated clock signal to be a value setby the frequency data. The order of the delta sigma modulation may befirst order, second order or higher order. However, the accuracy in thecase of second order is higher than that in the case of first order,-andin the case of third or higher order, the circuit is scaled up althoughthe effect is not so different from that in the case of second order.Therefore, about second order is desirable.

FIG. 3 shows a configuration example of the multiphase clock signalgenerating circuit 101 as shown in FIG. 1. The multiphase clock signalgenerating circuit 101 as shown in FIG. 3 has three differentialamplifiers 201 to 203 and six comparators 211 to 216. The threedifferential amplifiers 201 to 203 form a ring oscillator. The sixcomparators 211 to 216 compare non-inversion outputs and inversionoutputs of the differential amplifiers 201 to 203, which have delays, inthe comparators 211 to 216 to convert them into six-phase clock signalsCK1 to CK6. By setting all delay times of the differential amplifiers201 to 203 to be equal, the six-phase clock signals CK1 to CK6 can bemade at equal phase intervals.

FIG. 4 shows a configuration example of the multiphase VCO 116 as shownin FIG. 2. The multiphase VCO 116 as shown in FIG. 4 has a ringoscillator formed by six differential amplifiers 221 to 226 and twelvecomparators 231 to 242. By the control voltages of the differentialamplifiers 221 to 226, delay times at the respective differentialamplifiers can be changed and the frequency can be controlled. Further,by performing level conversion on the outputs of each differentialamplifier by using two comparators for normal and inversion,twelve-phase clock signals CLK1 to CLK12 are generated.

FIG. 5 shows a configuration example including the modulated clocksignal generating circuit 102 and the edge appearance time adjustmentcircuit 103 as shown in FIG. 1. As shown in FIG. 5, the edge appearancetime adjustment circuit 103 includes flip-flop circuits 801 to 806 andthe modulated clock signal generating circuit 102 includes switchcircuits 811 to 816 corresponding to the flip-flop circuits 801 to 806and a buffer circuit 821 commonly provided for outputs thereof.

To the respective input terminals of the flip-flop circuits 801 to 806,corresponding first group of clock selection signals SEL1 to SEL6 areinputted, and, to the clock signal terminals thereof, there are inputtedrespective clock signals CK1 to CK6 having a phase difference within apredetermined range from the clock signals selected in accordance withthe first group of clock selection signals SEL1 to SEL6. For example,the clock selection signal SEL1 is inputted to the input terminal of theflip-flop circuit 801 and the clock signal CK5 is inputted to the clocksignal terminal thereof. Similarly, the clock selection signal SEL2 isinputted to the input terminal of the flip-flop circuit 802 and theclock signal CK6 is inputted to the clock signal terminal thereof.

Thereby, the first group of clock selection signals SEL1 to SEL6inputted to the flip-flop circuits 801 to 806, respectively, are latchedin synchronization with respective clock signals having a phase leadingby T/3 (120 degrees) the clock signals CK1 to CK6 respectively selectedby the first group of clock selection signals SEL1 to SEL6, and thelatched signals are outputted as second group of clock selection signals(switch control signals) SSEL1 to SSEL6 for controlling ON/OFF of thecorresponding first to sixth switch circuits 811 to 816.

To prevent edge appearance times from overlapping between the secondgroup of clock selection signals SSEL1 to SSEL6 and respective clocksignals selected thereby, the widest margin is obtained in the casewhere the phase difference between the selected clock signal and theclock signal to be used for latching the first group of clock selectionsignals in the flip-flop circuits is set on about 90 degrees. FIG. 5shows the case where the phase difference is 120 degrees as an example.

To the input sides of the switch circuits 811 to 816, correspondingclock signals CK1 to CK6 are inputted, ON/OFF control is performedaccording to the second group of clock selection signals SSEL1 to SSEL6,and the selected one clock signal is transmitted to the output side. Theoutput sides of the switch circuits 811 to 816 are commonly connectedand the selected clock signal is outputted as a selected clock signalSELCLK via a buffer circuit 821.

FIG. 6 shows a configuration example including a twelve-phase modulatedclock signal generating circuit 102 and the edge appearance timeadjustment circuit 103. Since the edge appearance time adjustmentcircuit 103 adjusts the activation timing of second group of clockselection signals SSEL1 to SSEL12, the edge appearance times areconstantly at fixed intervals between the second group of clockselection signals and the selected respective clock signals, and theedges of both never overlap.

In the edge appearance time adjustment circuit 103, the first group ofclock selection signals SEL1 to SEL12 are latched in synchronizationwith respective clock signals having a predetermined phase differencefrom the corresponding clock signals CK1 to CK12, and outputted assecond group of clock selection signals SSEL1 to SSEL12 in which edgeshave been adjusted. The modulated clock signal generating circuit 102selects one of the clock signals CK1 to CK12 according to the secondgroup of clock selection signals SSEL1 to SSEL12 and outputs it as aselected clock signal SELCLK.

FIGS. 7A and 7B show configuration examples of the switch circuit 811within the modulated clock signal generating circuit 102 in FIG. 5. Theswitch circuit as shown in FIG. 7A is an analog switch of CMOS circuitsand has an N-channel MOS transistor 903, a P-channel MOS transistor 902and an inverter 901. To the control terminal (gate terminal) of theN-channel MOS transistor 903, one of the second group of clock selectionsignals (switch control signals), e.g., a clock selection signal SSEL1as shown in FIG. 5 is inputted. To the gate terminal of the P-channelMOS transistor 902, the clock selection signal SSEL1 inversed by theinverter 901 is inputted. When the clock selection signal SSEL1 is setat a high level, the analog switch becomes conductive and the clocksignal CK1 inputted to the analog switch is transmitted to the outputterminal OUT of the analog switch.

The switch circuit as shown in FIG. 7B employs an N-channel MOStransistor 904, and a clock selection signal SSEL1 is inputted to thegate terminal of the N-channel MOS transistor 904. When the second clockselection signal SSEL1 is at a high level, the clock signal CK1 inputtedto the switch circuit is transmitted to the output terminal OUT of theswitch circuit.

By the way, the switch circuits 812 to 816 and the switch circuits inFIG. 6 may be formed similarly to that shown in FIG. 7A or 7B.

FIG. 8 shows a modified example of the modulated clock signal generatingcircuit and the edge appearance time adjustment circuit as shown in FIG.5 or 6. In FIG. 8, differences from the configuration as shown in FIG. 5or 6 are in the point where, to the clock signal input terminal of aflip-flop circuit corresponding to the switch circuit 1011, a clocksignal CK1 same as a clock signal inputted to the corresponding switchcircuit 1011 is inputted, and the point where there is provided a delaycircuit 1002 for delaying the clock signal CK1 inputted to the switchcircuit 1011. Practically, N circuits as above-mentioned are provided.

In the case of employing the configuration as shown in FIG. 8, a clocksignal delayed by the delay circuit 1002 relative to the clock signalCK1 is similarly inputted to the switch circuit 1011, and therefore, aclock signal different in edge appearance time from the clock signal CK1inputted to the flip-flop circuit 1001 can be inputted to the switchcircuit 1011.

Referring to FIGS. 9 and 10, the operations of the above-mentionedmodulated clock signal generating circuit and edge appearance timeadjustment circuit will be described. In FIGS. 9 and 10, waveforms ofthe first group of clock selection signals SEL1 to SEL6, the secondgroup of clock selection signals SSEL1 to SSEL6 as substantial selectionsignals for selecting one of the clock signals CK1 to CK6 in FIG. 5, forexample, the clock signals CK1 to CK6 and the selected clock signalSELCLK are shown.

In FIG. 9, the clock signals CK1 to CK6 are shifted in the phase laggingdirection. According to the second group of clock selection signalsSSEL1 to SSEL6, one of the clock signals CK1 to CK6 is sequentiallyselected. The period of thus generated selected clock signal SELCLKbecomes T+ΔT.

The first group of clock selection signals SEL1 to SEL6 are signals insynchronization with the selected clock signal SELCLK. Accordingly, thesecond group of clock selection signals SSEL1 to SSEL6 are generated bylatching the first group of clock selection signals SEL1 to SEL6 insynchronization with other predetermined clock signals, respectively. Inthe example as shown in FIG. 9, with respect to the clock signal CK1, bylatching the first clock selection signal SEL1 in synchronization withthe rising edge of the clock signal CK5, the second clock selectionsignal SSEL1 is changed into at low level or high level. Further, withrespect to the clock signal CK2, by latching the first selection signalSEL2 in synchronization with the rising edge of the clock signal CK6,the second clock selection signal SSEL2 is changed into at low level orhigh level. Similarly, others of the second group of clock selectionsignals SSEL3 to SSEL6 are generated.

Here, as clearly seen in FIG. 9, edge appearance positions of the clocksignal CK1 and the second clock selection signal SSEL1 generated insynchronization with the clock signal CK5 having a different phase fromthe clock signal CK1 (leading in phase by T/3, i.e., 120 degrees) areconstantly at fixed intervals and the edge appearance times neveroverlap. Accordingly, with respect to the selected clock signal SELCLKsequentially generated by one of the clock signals CK1 to CK6, thewaveform of the selected clock signal never becomes deteriorated becausethe edge appearance times of the second group of clock selection signalsSSEL1 to SSEL6 and the edge appearance times of the respectivelyselected clock signals CK1 to CK6 never overlap even if the period T+ΔTcontinues so long. Thus, there is an advantage that selected clocksignals SELCLK corresponding to CK1→CK2→CK3→CK4→CK5→CK6→CK1→ . . . canbe continuously generated. In FIG. 9, there is a period in which all ofthe second group of clock selection signals SSEL1 to SSEL6 are at lowlevel, however, within the period, the outputs of the switch circuitsare held by parasitic capacitances of elements and wirings.

In FIG. 10, as well as in FIG. 9, one clock signal is sequentiallyselected from the clock signals CK1 to CK6. However, the case isdifferent in the point where the period of the generated selected clocksignal SELCLK is T−ΔT. That is, the clock signals CK1 to CK6 are shiftedin the phase leading direction. For example, as clearly seen in FIG. 10,edge appearance times of the clock signal CK1 and the clock selectionsignal SSEL1 generated based on the clock signal CK5 having a differentphase from the clock signal CK1 (leading in phase by T/3, i.e., 120degrees) are constantly at fixed intervals and the edge appearance timesnever overlap.

Accordingly, with respect to the selected clock signal SELCLKsequentially generated based on the clock signals CK1 to CK6, no problemarises however long the period T−ΔT continues. Thus, there is anadvantage that selected clock signals SELCLK respectively correspondingto CK1→CK2→CK3→CK4→CK5→CK6→CK1→ . . . can be continuously generated.Although the six-phase case has been described in the above description,they operate similarly in the twelve-phase case.

FIG. 11 shows a configuration example of a control circuit 104 forsupplying the clock selection signals to the edge appearance timeadjustment circuit 103. As shown in FIG. 11, the control circuit 104includes a control logic circuit 106 having a frequency data generator601 and a three-valued ΔΣ modulator 602, and a clock selection signalgenerating circuit 105 having an up/down ring register 603. The ringregister 603 causes the state transition in synchronization with theselected clock signal SECLK to generate the first group of clockselection signals SEL1 to SEL12. The frequency data FData outputted fromthe frequency data generator 601 is inputted to the three-valued ΔΣmodulator 602 and converted into a three-valued control signal CSG. Theup/down ring register 603 causes the selection transition forward orbackward, or maintains it according to the control signal CSG. Notethat, in the phase-selective type frequency modulator as shown in FIG.1, a period data generator is used in place of the frequency datagenerator.

FIG. 12 shows the up/down ring register 603 as shown in FIG. 11. Theup/down ring register 603 has D-type flip-flop circuits (D-FF) 501 to512 and selector circuits 521 to 532 corresponding to these flip-flopcircuits 501 to 512. The output terminals of the flip-flop circuits 501to 512 are connected to the input terminals of the first group of clockselection signals SEL1 to SEL12 in the edge appearance time adjustmentcircuit 103 (see FIG. 6), respectively.

The selector circuits 521 to 532 are formed of three-input one-outputselector circuits and controlled by the control signal (selector signal)CSG as an output of the control logic circuit 106 (see FIG. 11). Morespecifically, the selector circuits 521 to 532 are circuits foroutputting one of three inputs in accordance with the three conditionsof the control signal CSG. On the other hand, the flip-flop circuits 501to 512 latch the outputs of the selector circuits 521 to 532 insynchronization with the selected clock signal SECLK outputted from themodulated clock signal generating circuit and output them as the firstgroup of clock selection signals SEL1 to SEL12. Thereby, a signal athigh level transitions among the first group of clock selection signalsSEL1 to SEL12.

FIG. 13 shows another configuration example of the control circuit 104.The control circuit 104 includes a clock selection signal generatingcircuit 105 having an up/down counter 401 and a decoder 402, and acontrol logic circuit 106 for controlling the clock selection signalgenerating circuit 105. The clock selection signal generating circuit105 outputs the first group of clock selection signals SEL1 to SEL12 inaccordance with the value of the control signal supplied from thecontrol logic circuit 106. Simultaneously, the clock selection signalgenerating circuit 105 shifts the clock selection signal to be activatedto the forward one or backward one, or maintains without change inaccordance with the value of the control signal supplied from thecontrol logic circuit 106.

The control logic circuit 106 outputs a control signal CSG forcontrolling the up/down counter 401. The up/down counter 401 is acounter capable of incrementing or decrementing the value of the counterone at a time when receiving pulse. The up/down counter 401 operates insynchronization with the modulated clock signal (pulse signal) SELCLK,and changes the counter value CTV of the output at each time whenreceiving the control signal CSG such that 1→2→3→4→ . . . →11→12→1→2→ .. . (UP), or 12→11→ . . . →4→3→2→1→12→11→ . . . (DOWN).

The up/down counter 401 outputs a value corresponding to one of thethree operations of “UP”, “DOWN” and “HOLD” as a counter value CTV tothe decoder 402. The decoder 402 activates one of the first group ofclock selection signals SEL1 to SEL12 at a high level among the firstgroup of clock selection signals SEL1 to SEL12 in correspondence withthe counter value CTV.

FIG. 14 shows the operation of the control circuit 104 as shown in FIG.13. The operation of the control circuit 104 differs between the casewhere the value of the control signal CSG represents “UP” and the casewhere the value of the control signal CSG represents “DOWN”. In the casewhere the value of the control signal CSG represents “UP”, the signal ata high level among the first group of clock selection signals SEL1 toSEL12 changes such that SEL1 →SEL2→SEL3→ . . . as shown by an arrow AR1.On the other hand, in the case where the value of the control signal CSGrepresents “DOWN”, the signal at high-level among the first group ofclock selection signals SEL1 to SEL12 changes such that SEL4→SEL3→SEL2→. . . as shown by an arrow AR2.

FIG. 15 shows the configuration of the three-valued ΔΣ modulator 602 asshown in FIG. 11. As shown in FIG. 15, this ΔΣ modulation circuit has aquadratic configuration, and has a first to fourth adders 701, 702, 704and 705, delay circuits 703 and 706 and a three-valued quantizer 707.The three-valued quantizer 707 outputs one of the three values of +Δ, 0,−Δ as the control signal CS in response to the input. With respect tothe selection of clock signal, when three values are associated with“backward transition”, “maintenance” and “forward transition”, thefrequencies of the modulated clock signals are controlled to bef=f0·13/12, f=f0 and f=f0·11/12, respectively.

According to the configuration as shown in FIG. 15, by inputting thevalue expressed by the following expression as the frequency data FData,the frequency of the modulated clock signal MCK can be controlled to bean arbitrary frequency f1.Frequency data=Δ×(f 1−f 0)/(f 0/12)   (5)

Note that, in place of the three-valued ΔΣ modulator as shown in FIG.15, a one-bit ΔΣ modulator may be used. In this case, one bit isassociated with two of “backward transition”, “maintenance” and “forwardtransition”.

Thus, frequency modulation can be realized by a simple configuration.Further, generally, when the pulse width of the change pump is large,the jitter of the PLL output tends to be larger. On the other hand, inthe modulated clock signal generating circuit according to theembodiment, the phase of the clock signal for the feed back can befinely controlled by using the selector, and therefore, there is anadvantage that the jitter is reduced.

According to the above-mentioned modulated clock signal generatoraccording to the first embodiment of the present invention, modulatedclock signals with no restriction on the phase valuable range can begenerated and the EMI of electronic equipment can be reduced.

Next, a phase-selective type frequency modulator according to a secondembodiment of the present invention will be described by referring toFIG. 16. As shown in FIG. 16, the phase-selective type frequencymodulator according to the second embodiment has a multiphase clocksignal generating circuit 101, a modulated clock signal generatingcircuit 102, an edge appearance time adjustment circuit 103 and acontrol circuit 104 as well as the phase-selective type frequencymodulator according to the first embodiment as shown in FIG. 1. Itdiffers from the circuit as shown in FIG. 1 in the point where a PLL1205 is additionally connected to the output of the modulated clocksignal generating circuit 102. In the embodiment, a modulated clocksignal MCK is outputted from the PLL 1205. According to the embodiment,the discrete cyclic change in the selected clock signal SELCLK outputtedfrom the modulated clock signal generating circuit 102 is filtered by aloop filter of the PLL 1205, and therefore, a modulated clock signal inwhich frequency change is mild can be obtained.

INDUSTRIAL APPLICABILITY

The present invention can be utilized in a phase-selective typefrequency modulator and a phase-selective type frequency synthesizer tobe used in electronic equipment for performing transmission of imagedata and so on.

1. A phase-selective type frequency modulator comprising: multiphaseclock signal generating means for generating N-phase clock signalshaving phase differences from each others; control means forsequentially activating one of first group of clock selection signalsindicating a clock signal to be selected from the N-phase clock signalsoutputted from said multiphase clock signal generating means, said firstgroup of clock selection signals corresponding to said N-phase clocksignals; edge appearance time adjusting means for adjusting a risingedge appearance time and/or a trailing edge appearance time of the firstgroup of clock selection signals outputted from said control means tooutput second group of clock selection signals corresponding to theN-phase clock signals outputted from said multiphase clock signalgenerating means; and modulated clock signal generating means forselecting one clock signal from said N-phase clock signals in accordancewith an activated state of said second group of clock selection signalsoutputted from said edge appearance time adjusting means to output theselected clock signal as a modulated clock signal.
 2. A phase-selectivetype frequency modulator comprising: multiphase clock signal generatingmeans for generating N-phase clock signals having phase differences fromeach others; control means for sequentially activating one of firstgroup of clock selection signals indicating a clock signal to beselected from the N-phase clock signals outputted from said multiphaseclock signal generating means, said first group of clock selectionsignals corresponding to said N-phase clock signals; edge appearancetime adjusting means for adjusting a rising edge appearance time and/ora trailing edge appearance time of the first group of clock selectionsignals outputted from said control means to output second group ofclock selection signals corresponding to the N-phase clock signalsoutputted from said multiphase clock signal generating means; modulatedclock signal generating means for selecting one clock signal from saidN-phase clock signals in accordance with an activated state of saidsecond group of clock selection signals outputted from said edgeappearance time adjusting means to output the selected clock signal; andPLL (phase locked loop) means for receiving the clock signal selected bysaid modulated clock signal generating means and filtering jitter in theselected clock signal to output a modulated clock signal.
 3. Aphase-selective type frequency modulator according to claim 1, whereinsaid edge appearance time adjusting means adjusts the rising edgeappearance time and/or the trailing edge appearance time of said firstgroup of clock selection signals such that a rising edge appearance timeand/or a trailing edge appearance time of the clock signal selected inaccordance with the first clock selection signal activated by saidselecting means and a rising edge appearance time and/or a trailing edgeappearance time of said second group of clock selection signals may notoverlap.
 4. A phase-selective type frequency modulator according toclaim 2, wherein said edge appearance time adjusting means adjusts therising edge appearance time and/or the trailing edge appearance time ofsaid first group of clock selection signals such that a rising edgeappearance time and/or a trailing edge appearance time of the clocksignal selected in accordance with the first clock selection signalactivated by said selecting means and a rising edge appearance timeand/or a trailing edge appearance time of said second group of clockselection signals may not overlap.
 5. A phase-selective type frequencysynthesizer comprising: control means for sequentially activating one offirst group of clock selection signals indicating a clock signal to beselected from N-phase clock signals having phase differences from eachothers, said first group of clock selection signals corresponding tosaid N-phase clock signals; edge appearance time adjusting means foradjusting a rising edge appearance time and/or a trailing edgeappearance time of the first group of clock selection signals outputtedfrom said control means to output second group of clock selectionsignals corresponding to said N-phase clock signals; modulated clocksignal generating means for selecting one clock signal from said N-phaseclock signals in accordance with an activated state of said second groupof clock selection signals outputted from said edge appearance timeadjusting means to output the selected clock signal; phase comparingmeans for comparing a phase of a reference clock signal and a phase ofthe clock signal selected by said modulated clock signal generatingmeans; and multiphase clock signal generating means for generating saidN-phase clock signals based on a comparison result in said phasecomparing means and outputting one of said N-phase clock signals as amodulated clock signal.
 6. A phase-selective type frequency synthesizeraccording to claim 5, further comprising dividing means forfrequency-dividing the clock signal selected by said modulated clocksignal generating means and outputting the frequency-divided clocksignal to said phase comparing means.